The course aims to introduce students to the field of adaptable and reconfigurable computing systems based on FPGAs, discussing the system architecture, the different design flows, and how to interact with them.  To cope with the continuously evolving innovation pace, user mutation needs, system requirements changes, communication protocols and data encoding updates, system revisions, and requests to support different user applications, many emerging in communication, information technology, and consumer electronics, the producers have to design systems flexible at the hardware level after manufacturing. Therefore, adaptive computing systems are a unique opportunity to deliver highly optimized and hardware-level reconfigurable silicon that guarantees domain specialization and flexibility. Indeed, they are becoming ubiquitous and essential in many fields. The course aims to give a methodological approach to such systems to demystify such complex systems and empower the new designer with engineering decisions on HW/SW co-design trade-offs. The main topics revolve on introduction to adaptable and reconfigurable systems and FPGAs, Vivado and Vitis HLS design flows; then the course involves three orthogonal modules which focus on specific systems, their design flows, and how to interact with them and they are: Edge Reconfigurable System On Chip, HPC Accelerator Cards, AI Inference Accelerators. At the end of the course, students must carry on a teaching-like project to complete their course (optionally in team of up to 2 participants), agreed with the teacher. Students willing to pursue more advanced hard skills in the FPGA and Adaptive Systems path can continue in the following semester in the context of the Xilinx Open Hardware design contest (http://www.openhw.eu/). The Xilinx Open Hardware, XOHW, is a design contest at the European and Asian level, born in 2015 and promoted by Xilinx, and sees FPGAs at the center of project development by teams of up to 3 participants. As Politecnico di Milano we have participated since 2016, and since then, we have arrived among the finalists several times. With this course, we want to open to all Politecnico's students the opportunity to participate in this competition supported by domain experts and students who have already participated and won the XOHW. In this way, we aim to create a heterogeneous context where this feature will help the development of innovative ideas to then be carried out in various projects.

dal March 2024 a May 2024

Le aule saranno comunicate e visibili sul calendario del corso: tinyurl.com/PiAatDEIB

Per le lezioni di questo corso si cerchi #FPGA101Tutte le lezioni sarano dalle 6pm alle 7.30pm/8pm
18/03/2024 Intro to FPGA101, FPGA technology, and design flows; PT1 Room Building 20 - Ground Floor
21/03/2024 Vivado Design Suite; PT1 Room Building 20 - Ground Floor
25/03/2024 VHDL-based Design Flow; PT1 Room Building 20 - Ground Floor
28/03/2024 Vitis High Level Synthesis; PT1 Room Building 20 - Ground Floor
04/04/2024 Vitis Software Theory; PT1 Room Building 20 - Ground Floor
08/04/2024 Vitis Software Practice; PT1 Room Building 20 - Ground Floor
11/04/2024 PYNQ and SoCs Theory; PT1 Room Building 20 - Ground Floor
15/04/2024 PYNQ and SoCs Practice; PT1 Room Building 20 - Ground Floor
18/04/2024 NetFPGA; Sala Conferenze Emilio Gatti Room Building 20 - Ground Floor
22/04/2024 Versal Adaptive SoC; PT1 Room Building 20 - Ground Floor
29/04/2024 Project presentation; PT1 Room Building 20 - Ground Floor
15/05/2024 Q&A; PT1 Room Building 20 - Ground Floor