Department of Electronics, Information and Bioengineering
DESIGN OF INTEGRATED CIRCUITS FOR MEMRISTIVE NEURAL NETWORKS NELL'AMBITO DEL PROGETTO MIUR/FARE/DEEPEN-BANDO 2016/R164TYLBZP (CUP:D42F17001240007)//THE ACTIVITY IS AIMED AT THE DEVELOPMENT OF VERILOG-A MODELS FOR MEMRISTIVE DEVICES AND THE DESIGN OF INTEGRATED NEURAL NETWORKS WITH MEMRISTIVE ELEMENTS -2018_ASSEGNI_DEIB_6
Deadline: 28-02-18
Interview: 14-03-18
Some documents related to this call are available in Italian only