Memristive circuit for random number generation and physically unclonable function

Data di pubblicazione




Data di priorità



Patent application in Europe and US


Politecnico di Milano


Department of Electronics, Information and Bioengineering


Daniele Ielmini, Simone Balatti, Stefano Ambrogio,


The invention consists of a novel approach for true random number generation (TRNG), also capable of achieving a physical unclonable function (PUF) for hardware security. The objective is met by using 2 memristors in a circuit with serial/parallel configuration, where a random bit is generated by the application of a standard pulse across the memristors, and the bit value results from the comparison between the resistances of the 2 memristors during the read operation. The 2-memristor configuration intrinsically guarantees the uniformity of bit values, namely the probabilities of generating either 0 or 1 are both 50%. The generation of random bits can be repeated an arbitrary number of times for TRNG applications, or can be executed only once to generate a hardware signature of a circuit for PUF applications (e.g., chip security and counterfeits). The unicity of the signature is guaranteed by the intrinsic stochastic variation of the memristor operation.

Campo di applicazione

The invention finds application in systems-on-chip (SoC) requiring generation of random numbers for cryptography application or containing a hardware signature for the purpose of security of the transmitted information. Given the growing amount of systems on chip for internet-of-things (IoT) applications with transmission of sensitive data, there is a significant interest in TRNG and PUF functions with high density, low cost, low power consumption, and meeting the requirements of uniformity, unicity and reliability.


The 2-memristors layout guarantees the uniformity (50% probability) of generated bits irrespective of the applied voltage. This approach overcomes the limitations of 1-memristor schemes, which require instead a pre-calibration of the voltage to ensure equal probability of 0 or 1, hence a higher circuit complexity and higher cost.

Stadio di sviluppo

Preliminary Prototype