HETEROGENEOUS ARCHITECTURES DESIGN CONTEST

(Informatic laboratory, Frontal teaching)

  • Language: ENGLISH
  • Campus: MILANO CITTÀ STUDI
  • Enrollment: 17-03-2023to hour 12:00 on
    10-04-2023
  • Subject area: Tech and society
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Teacher in charge
SANTAMBROGIO MARCO DOMENICO
Credits
2
Hours to attend
10
Prerequisites
  • Basic knowledge of computer architectures
  • Programming expertise, preferably also in object-oriented languages
Max. number of students
100
Selection Criteria
  • Precedence will be given to students who attended the courses "Architetture dei Calcolatori e Sistemi Operativi" and "Advanced Computer Architectures"
  • Precedence will be given to students who demonstrate knowledge in hardware design and FPGA
Topics:
Computer Architecture, RISC-V, digital design
Tag
Computer science, Engineering

Description of the initiative

The end of Moore's law is causing a shift in the world of computer architectures. Homogeneous single-core and multi-core CPUs are steadily giving way to heterogeneous computing systems boasting a collection of specialized components. This pervasive trend is affecting every sector of the market, from mobile to desktop, all the way to high-end servers for data centers. Hardware specialization is the golden ticket to high performance, be it for graphics processing, AI, or any other relevant application domain. In this course, students will learn to design System on Chip for specialized application domains through Chipyard, a RISC-V-based open framework for SoC generation. The course will cover basic digital design in the Chisel language, a modern object-oriented hardware construction language, and will teach students how to generate a customized SoC using the Chipyard framework's components, which include several RISC-V CPUs and domain-specific accelerators. Students will then be asked to design a custom SoC specialized for one of two application domains that will be presented during the course. The final goal of the contest is to design and prototype a custom SoC, maximizing the performance given a target algorithm and dataset under the resource constraints of the target prototyping system.

Duration

dal April 2023 a June 2023

Calendar

Il calendario del corso è visibile sul calendario: tinyurl.com/PiAatDEIBPer le lezioni di questo corso si cerchi #HADC

  • 13/04/2023 - 18:00/20:00
  • 20/04/2023 - 18:00/20:00
  • 27/04/2023 - 18:00/20:00
  • 04/05/2023 - 18:00/20:00
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